embedded news: Arm Morello, Digital Security by Design, OpenHW Group
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A key news story this week is Arm’s new chip and demonstrator board containing the first example of its Morello prototype, based on the CHERI architecture that defines hardware capabilities to provide a fundamentally more secure building block for software. This is the result of ongoing research to look […]

Click here to view original web page at www.embedded.com


A key news story this week is Arm’s new chip and demonstrator board containing the first example of its Morello prototype, based on the CHERI architecture that defines hardware capabilities to provide a fundamentally more secure building block for software. This is the result of ongoing research to look at addressing fundamental vulnerabilities in computer systems architectures, which resulted in the CHERI (Capability Hardware Enhanced RISC Instructions) protection model, now implemented by Arm in its Morello board.

Arm morello chip
(Image: Arm)

I spoke this week to industry veteran and professor of computer architecture John Goodacre, in his role as challenge director for an initiative called Digital Security by Design (DSbD), who explained the background to CHERI, and the role of DSbD in helping bring some of this research to market. He said, “We need to stop the exploitation of vulnerabilities. By design we can change the design of the CPU so that these vulnerabilities cannot be exploited.” Look out for more on this in coming weeks, but meanwhile you can read about the latest development by Arm in this project here, and more background in a piece I wrote in 2019 here.

Also this week I had my annual January fireside chat with Rick O’Connor, CEO of OpenHW Group, to talk about developments in and key drivers in the growth of open-source processor development, plus the latest milestones and projects of the OpenHW Group. It will air 27th January with a live Q&A, and you can register here.

In new articles this week, we look at understanding and using No-OS and platform drivers, the building blocks of artificial vision and why Open RAN needs a zero-trust approach to cybersecurity. In addition, Ian Ferguson of Lynx Software Technologies asks, are we ready for open-source software in safety-critical embedded systems?, and key executives from Synopsys explore trends driving the future of high-performance computing (HPC).

News and products on the web site, there’s plenty to read, including Khronos and EMVA calling for participants for developing an open API for embedded cameras, Cartier launching a new solar watch using an energy harvesting power management IC, plus Samsung’s new ray tracing mobile processor and Mauna Kea Semiconductors launching an integrated low power UWB SoC for precision sensing.

And below, you’ll find more news from Renesas Electronics, Cadence Design Systems, Siemens Digital Industries Software, United Microelectronics Corporation (UMC), Imagination Technologies, Andes Technology, Abaco Systems, Green Hills Software, Amcor, PragmatIC Semiconductor, and Blueshift Memory.

News & Products

Renesas one billion RX MCU
(Image: Renesas)

Renesas Electronics said it has delivered more than one billion microcontrollers from the RX family of 32-bit MCUs, which incorporate Renesas’ proprietary RX CPU core. Since its launch in 2009, the RX family has been adopted in a wide range of consumer, industrial, and IoT applications. Currently, four series of RX MCUs are available (RX100, RX200, RX600, and the high-end RX700) offering a wide range of performance, on-board memory, and a variety of peripheral functions and packages. Following the introduction of the latest RXv3 core in 2018, Renesas is also working on the development of the next core with the aim of surpassing the performance of the RXv3 core.

Cadence Design Systems announced a new DRAM verification solution, allowing customers to test and optimize system-on-chip (SoC) designs for data center, consumer, mobile and automotive applications. Using the full DRAM verification solution, which delivers up to 10X increased verification throughput, customers can quickly and effectively perform IP-to-SoC-level verification of advanced designs with multiple DDR interfaces. It enables IP-level verification through Cadence PHY VIPs and memory models with a direct and seamless path to SoC-level verification with the Cadence System VIP solution, with built-in integration and content for DRAM interfaces, enabling fast and efficient memory subsystem and SoC verification for simulation and emulation environments.

Siemens UMC design kits
(Image: Siemens Digital Industries Software)

Siemens Digital Industries Software announced a collaboration with United Microelectronics Corporation (UMC) to develop process design kits (PDKs) for the foundry‘s 110-nm and 180-nm BCD technology platforms. The new PDKs for UMC, a foundry focused on logic and specialty technologies, are optimized for Siemens EDA’s Tanner custom design flow software, enabling innovative designs for a wide variety of ICs used in automotive and power applications. Siemens‘ Tanner software features an advanced, high-performance, easy-to-use schematic and layout editor and integration with best-in-class circuit simulators and Calibre software, a solution for design rule checking, parasitic extraction and physical verification.

Imagination Technologies and Andes Technology have successfully tested and validated the IMG B-Series GPU with the RISC-V compliant Andes AX45, a 64-bit highly performance-efficient and configurable superscalar CPU. This validation partnership offers customers in AR/VR, in-vehicle infotainment (IVI) systems, and industrial and IoT products, a proven and complete solution and lays the groundwork for continuous testing. The IMG BXE-2-32 GPU was validated alongside the Andes AX45 CPU as a part of a FPGA platform, containing networking, memory and peripherals. The FPGA rendered numerous graphics workloads and benchmarks using a Linux based operating system. This FPGA demonstrates the flexibility of the IMG B-Series GPU and the interoperability of the Andes AX45 RISC-V CPU.

Mediatek said it has shown the world’s first live demo of Wi-Fi 7 technology, showcasing it to key customers to demonstrate the technology’s super-fast speeds and low latency transmission. The demo shows how its Wi-Fi 7 Filogic technology can achieve the maximum speed defined by IEEE 802.11be and demonstrates its multi-link operation (MLO) technology. MLO technology aggregates multiple channels on different frequencies bands at the same time to highlight how network traffic can still flow seamlessly even if there is interference or congestion on the bands. MLO technology will be critical for delivering faster and more reliable video streaming, gaming and anything else that requires constant, sustained and real-time throughput.

Green Hills Software - Abaco
(Image: Green Hills Software)

Abaco Systems and Green Hills Software announced that the rugged, 3U VPX SBC3511 single board computer supports the INTEGRITY-178 tuMP real-time operating system (RTOS) for avionics and security-critical applications. The combined solution features a Modular Open Systems Approach (MOSA) that is aligned to the SOSA technical standard and certified to the FACE technical standard. Together the products address requirements of security-critical systems including both functional security and assurance requirements. Additionally, INTEGRITY-178 was certified to the NSA-defined separation kernel protection profile (SKPP) high-robustness security and Common Criteria EAL 6+, and INTEGRITY-178 tuMP is the first and only RTOS to be part of a cross-domain solution (CDS) certification to NSA’s new “Raise the Bar” standards.

Funding

PragmatIC FlexLogIC image_web
(Image: PragmatIC Semiconductor)

Packaging firm Amcor announced a strategic $5 million investment in PragmatIC Semiconductor, a developer of flexible, integrated circuits beyond the scope of conventional electronics, as part of a $90 million series C funding round for PragmatIC. Its ConnectIC family of radio frequency identification and near-field communications (RFID/NFC) ICs can be embedded into packaging to store and relay information to devices such as smartphones. This technology will enable smart packaging applications across the entire product lifecycle – from manufacturing and supply chain management to consumer engagement and even material recovery.

People

Blueshift Memory has appointed three new members to its board of advisors: Rupert Baines, Dr Ron Black and Guillaume d’Eyssautier. Baines was previously with UltraSoC and Picochip, Black was with Imagination Technologies and Rambus, and d’Eyssautier is a serial entrepreneur and investor in the semiconductor industry. Blueshift Memory has developed a proprietary chip design which optimizes the memory architecture for more efficient handling of large data sets and time-critical data, which the company says enables up to 1,000 times faster memory access for specific data-focused applications.

Events

The Things Conference Embedded 2022 (online), Friday 28 Jan 2022: a day dedicated to firmware and hardware development for LoRaWAN devices.

Design Automation Conference (DAC) announced preliminary numbers for its hybrid conference held last month in San Francisco. It said 2,256 badges were picked up at the live event at the venue, with total registrations of 3,521. DAC returns to San Francisco on 10-14 July 2022, co-located with SEMICON West. The engineering tracks call for contributions is now open. The final program will be available and advance registration will open early April 2022.

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